1. Field of the Invention
The present invention relates to a semiconductor memory device and method, and in particular, to a semiconductor memory device and method with enhanced data output speed.
2. Background of the Related Art
Various types of semiconductor memory devices are used in a computer system or other program driving system. Common memory devices include DRAM and SRAM. SRAM is very fast but expensive because of a low degree of integration. Therefore, DRAM is generally used in personal computers where the relatively low price and low speed are acceptable.
FIG. 1 is a block diagram showing the structure of a semiconductor memory cell array and peripheral circuits of a related art DRAM. As shown in FIG. 1, a row decoder 11 decodes a row address to select and activate a word line of a memory cell array 12. When a word line of the memory cell array 12 is activated, a column decoder 14 decodes a column address to select a bit line of the memory cell array 12. Sense amplifier 13 sequentially senses and amplifies data in a memory cell connected to the activated word line and then transmits the data to a data output buffer (not shown) through a data bus sense amplifier 15.
FIG. 2 is a circuit diagram depicting a memory cell of the memory cell array 12. The general structure of the memory cell includes a transistor and a capacitor. As shown in FIG. 2, a memory cell MCI has a structure with a capacitor C1 connected between the drain of NMOS transistor Q1 and ground. The source of NMOS transistor Q1 is connected to bit line BIT and the gate to the word line WLn.
As shown in FIG. 2, another memory cell MC2 includes an NMOS transistor Q2 and a capacitor C2. The gate of NMOS transistor Q2 is connected to a word line WLn+1 and the source to a bit line /BIT. As described above, when the word line WLn is activated, the NMOS transistor Q1 is turned on. When the word line WLn+1 is activated, the NMOS transistor Q2 is turned on.
The capacitors C1 and C2 are charged or discharged in accordance with the logic value of data. For example, when the word lines WLn and WLn+1 are respectively activated in a data read mode, the data charged is discharged through the turned on NMOS transistors Q1 and Q2. The discharged data is applied to the bit lines BIT and /BIT so that the bit lines BIT and /BIT vary in voltage. If the capacitors are not charged, there is no change in the voltage of the bit lines BIT and /BIT.
The two bit lines BIT and /BIT are precharged with a voltage of VCC/2. When the NMOS transistors Q1 and Q2 of the memory cells MC1 and MC2 are turned on so that the data of the capacitors C1 and C2 are respectively transmitted to the bit lines BIT and /BIT, the sense amplifier 13 compares the voltage difference between the two bit lines BIT and /BIT, and amplifies the voltage difference.
Referring to FIGS. 1 to 3, the data read operation of the related art semiconductor memory device will now be described. FIG. 3 is a timing chart showing the read operation of a related art semiconductor memory device. The case data of "0" being stored in the memory cell will be described as an example.
FIG. 3(a) shows a row address strobe signal /RAS and FIG. 3(b) shows a column address strobe signal /CAS. FIG. 3(c) shows a write enable signal /WE and FIG. 3(d) shows a word line voltage. FIG. 3(e) shows voltages of a pair of bit lines BIT and /BIT. FIG. 3(f) shows a bit line selection signal CD transmitted from the column decoder 14.
The row address strobe signal /RAS indicates that the row address is input. The column address strobe signal /CAS indicates that the column address is input. The write enable signal /WE controls the read and write operations of the memory device. A high level of the write enable signal /WE causes the write operation and a low level causes the read operation.
Time t0 is a stand-by state of the timing charts of FIGS. 3(a)-3(f) where the voltage of the word line is low. As described with respect to FIG. 2, the two bit lines BIT and /BIT of the memory cell are pre-charged with the potential VCC/2 or half of the power voltage VCC.
At time t1, the two bit lines BIT and /BIT of FIG. 2 are in a floating state that is not affected by an outside environment. Accordingly, the two bit lines BIT and /BIT sustain the precharge potential VCC/2.
At time t2, the row decoder 11 decodes the row address transmitted from the outside to select word line (e.g., WLn). The row decoder 11 increases the voltage of the selected word line to the sum of the supply voltage VCC and a MOS transistor threshold voltage, Vt. In other words, the voltage level VCC+Vt, is a word line activation level that activates the word line (e.g., WLn).
The NMOS transistor Q1, whose gate is connected to the activated word line WLn, is turned on so that the data stored in the capacitor C1 is applied to the bit line BIT. As shown in FIG. 3, the data of the capacitor C1 is "0". The charges are applied to the bit line BIT in accordance with the data of the capacitor C1 so that the potential of the bit line BIT becomes a potential slightly lower or slightly higher than the precharge voltage VCC/2. The bit line /BIT sustains the precharge voltage VCC/2. Thus, the potential of a bit line to which a cell to be read is connected is changed and the bit line not connected to the cell to be read remains VCC/2. Accordingly, a specified potential difference exists between the two bit lines BIT and /BIT. The sense amplifier 13 is activated to amplify the potential difference between the bit lines BIT and /BIT between time point t3 and time point t4.
When the amplification by the sense amplifier 13 is achieved to some degree (e.g., between t5 and t6), the ground voltage VSS is applied to the bit line BIT and the supply voltage VCC is applied to the bit line /BIT. Thus, the voltage "0" or the potential of the ground voltage VSS is stored by the capacitor C1 through the NMOS transistor Q1, which is turned on by the high level voltage of the word line WLn. As the result, the data can be read and the refresh operation is performed (i.e., data is rewritten).
Such operations are executed when the data stored in the capacitor C1 is "0". If the data of the capacitor C1 is "1", the opposite operations are performed.
If the amplification operation of the sense amplifier 13 is achieved to some degree so the potential difference between the two bit lines BIT and /BIT exceeds the sum of the respective threshold voltages of usual PMOS and NMOS transistors or ".vertline.Vtn.vertline.+.vertline.Vtp", a signal of the bit line BIT corresponding to the bit line selection signal CD is transmitted to the data output buffer using the data bus sense amplifier 15 via a data bus.
The data from the bit line is transmitted to the data output buffer through a data bus, which is connected to the bit line. The respective data buses switch according to the column address transmitted from the column decoder 14.
The data bus sense amplifier 15 amplifies the data that is transmitted from the bit line to the data bus, before transmitting it to the data output buffer. When the data transmission is completed, the data bus is precharged.
At time point t7, the word line WLn is deactivated to sustain the data stored in the capacitor C1 (e.g., by the refresh operation previously described). At time t8, for succeeding data output operations, the two bit lines BIT and /BIT are equalized by the precharge voltage VCC/2. Thus, the bit lines BIT and /BIT are placed in the stand-by state.
The series of data output operations in a related art semiconductor memory device as described above are performed with the deactivation operation of the word line whose data output is completed, and the activation of another word line whose new data will be output.
Thus, after the data transmission is completed from the activated word line, the precharge voltage is applied to the respective bit lines. Further, another word line cannot be activated until the voltage of the word line is lowered to the ground potential. Accordingly, related art semiconductor memory devices, especially DRAM, have slow data output speeds.